1. Field of the Invention
This invention generally relates to semiconductor devices and processes and more specifically to a method of fabricating and processing P-channel transistors in silicon layers formed on insulating substrates to obtain devices having high degrees of total dose radiation hardness.
2. Description of Related Art
Metal oxide semiconductor (MOS) technology is virtually the standard for digital circuits used in computers and telecommunication devices today. Increasingly, CMOS (complementary MOS) technology is utilized in these applications. CMOS technology incorporates both N-channel MOS and P-channel MOS transistors in the same monolithic structure.
“Radiation hardness” refers to the ability of a semiconductor device to withstand ionizing radiation without significant alteration of its electrical characteristics. A semiconductor device is said to be radiation hardened (rad-hard), radiation tolerant, or radiation resistant if it can continue to function within specifications after exposure to a specified amount and type of radiation. Semiconductor devices can be damaged or destroyed by the effects of ionizing radiation from natural and man-made sources. Radiation changes the electrical properties of solid state devices, leading to possible failure of any system incorporating them. Applications for radiation hardened semiconductor devices include use in harsh environments such as outer space, nuclear reactors, and particle accelerators. Additionally, improved radiation hardness is growing increasingly useful as semiconductor processing employs more manufacturing processes that generate radiation. For example, processing techniques such as reactive ion etching and plasma etching may introduce some radiation damage into the fabricated semiconductor structure.
The effect of ionizing radiation on MOS transistors is well known. The dominant effect is the charging of insulating layers adjacent to the semiconductor regions as a result of exposure to ionizing radiation. These charging effects have been widely studied, and mathematical models have been developed which provide a reasonable amount of predictive capability of the effect of ionizing radiation on the operation of an MOS device.
The induced charges can be categorized as one of two principal types, fixed oxide charges and interface state charges. Fixed oxide charges are incapable of exchanging charges with the semiconductor, and hence their charge density is insensitive to the position of the Fermi level in the adjacent semiconductor region. The second type, interface state charges, do exchange charges with the semiconductor layer and hence are sensitive to the position of the Fermi level in the adjacent semiconductor material. Both types of charges may or may not be produced in significant numbers as a result of the device being exposed to ionizing radiation. The two types of charges may occur separately or together.
There are several factors that determine the sensitivity of an MOS device to ionizing radiation exposure. Some of these factors include the dimensions of the device (W/L), the doping levels used in the construction of the device, the thicknesses of the insulating layers, and the electric fields across various regions of the device during the period of time that it is being exposed to the ionizing radiation environment.
In an effort to improve the performance of MOS devices, the art has focused on Semiconductor-On-Insulator (SOI) technology. In SOI technology, the devices are formed in a monocrystalline semiconductor layer, which is formed on an insulating layer which provides device isolation. While both conventional bulk CMOS devices and SOI CMOS devices may show degradation as a result of exposure to ionizing radiation, in SOI devices there are additional insulating layers (compared to bulk transistors) that can become charged as a result of radiation exposure.
It is well known that the so-called back interface of an SOI transistor can be very sensitive to ionizing radiation. In general, the charges that result are positive fixed charges in the back insulating layer. Since a positive oxide charge images a negative charge in the adjoining silicon region, the effect of such positive charge on the device operation can be readily understood.
In particular, for an N-channel transistor, the effect of such positive charge is to induce electrons at the back interface between the semiconductor layer and the insulating substrate. This will result in current flow between the source and drain of the transistor, even without the presence of a gate bias. This current is widely called “back channel” current to denote the fact that it is flowing near the back interface and is not capable of being controlled by the MOSFET gate. Similarly, it can be seen that positive charges in the back interface of a P-channel device will image negative charges in such a device, but that these negative charges will not result in any current flow in a P-channel transistor. Conversely, negative charges in such a back insulator image positive charges into the adjacent semiconductor region, causing current flow in a PMOS device, but no current flow in an NMOS device.
Previously, silicon-on-insulator (SOI) has been used for high performance microelectronics. The desirability of SOI devices for applications requiring radiation hardness is well-recognized. Fabrication of devices on an insulating substrate requires that an effective method for forming silicon CMOS devices on the insulating substrate be used. The advantages of using a composite substrate comprising a monocrystalline semiconductor layer, such as silicon, epitaxially deposited on a supporting insulating substrate, such as sapphire, have been well-recognized. These advantages include the substantial reduction of parasitic capacitance between charged active regions and the substrate and the effective elimination of leakage currents flowing between adjacent active devices. This is accomplished by employing an insulating material as the substrate, such as sapphire (Al2O3), spinel, or other known highly insulating materials, and providing that the conduction path of any interdevice leakage current must pass through the substrate.
An “ideal” silicon-on-insulator wafer may be defined to include a completely monocrystalline, defect-free silicon layer of sufficient thickness to accommodate the fabrication of active devices therein. The silicon layer would be adjacent to an insulating substrate and would have a minimum of crystal lattice discontinuities at the silicon-insulator interface. Early attempts to fabricate this “ideal” silicon-on-insulator wafer were frustrated by a number of significant problems, which can be summarized as (1) substantial incursion of contaminants into the epitaxially deposited silicon layer, especially the p-dopant aluminum, as a consequence of the high temperatures used in the initial epitaxial silicon deposition and the subsequent annealing of the silicon layer to reduce defects therein; and (2) poor crystalline quality of the epitaxial silicon layers when the problematic high temperatures were avoided or worked around through various implanting, annealing, and/or regrowth schemes.
It has been found that these high quality silicon films suitable for demanding device applications can be fabricated on insulating substrates by a method that involves epitaxial deposition of a thin silicon layer on an insulating substrate, low temperature ion implant to form a buried amorphous region in the silicon layer, and annealing the composite at temperatures below about 950° C. Sapphire is a very suitable and advantageous insulating substrate; though other oxide materials such as spinel may be employed. Examples of and methods for making such silicon-on-sapphire devices are described in U.S. Pat. No. 5,416,043 (“Minimum charge FET fabricated on an ultrathin silicon on sapphire wafer”); U.S. Pat. No. 5,492,857 (“High-frequency wireless communication system on a single ultrathin silicon on sapphire chip”); U.S. Pat. No. 5,572,040 (“High-frequency wireless communication system on a single ultrathin silicon on sapphire chip”); U.S. Pat. No. 5,596,205 (“High-frequency wireless communication system on a single ultrathin silicon on sapphire chip”); U.S. Pat. No. 5,600,169 (“Minimum charge FET fabricated on an ultrathin silicon on sapphire wafer”); U.S. Pat. No. 5,663,570 (“High-frequency wireless communication system on a single ultrathin silicon on sapphire chip”); U.S. Pat. No. 5,861,336 (“High-frequency wireless communication system on a single ultrathin silicon on sapphire chip”); U.S. Pat. No. 5,863,823 (“Self-aligned edge control in silicon on insulator”); U.S. Pat. No. 5,883,396 (“High-frequency wireless communication system on a single ultrathin silicon on sapphire chip”); U.S. Pat. No. 5,895,957 (“Minimum charge FET fabricated on an ultrathin silicon on sapphire wafer”); U.S. Pat. No. 5,920,233 (“Phase locked loop including a sampling circuit for reducing spurious side bands”); U.S. Pat. No. 5,930,638 (“Method of making a low parasitic resistor on ultrathin silicon on insulator”); U.S. Pat. No. 5,973,363 (“CMOS circuitry with shortened P-channel length on ultrathin silicon on insulator”); U.S. Pat. No. 5,973,382 (“Capacitor on ultrathin semiconductor on insulator”); and U.S. Pat. No. 6,057,555 (“High-frequency wireless communication system on a single ultrathin silicon on sapphire chip”).
By the methods described in the patents listed above, electronic devices can be formed in an extremely thin layer of silicon on an insulating substrate such as an insulating synthetic sapphire wafer. The thickness of the silicon layer is typically less than 150 nm. Such an “ultrathin” silicon layer maximizes the advantages of the insulating sapphire substrate and allows the integration of multiple functions on a single chip. In these devices, referred to herein as “ultrathin silicon-on-sapphire” devices, traditional transistor isolation wells required for thick silicon are unnecessary, simplifying transistor processing and increasing circuit density.
CMOS circuits have been fabricated on ultrathin silicon-on-sapphire substrates prepared by the methods described in the aforementioned patents. Such ultrathin silicon-on-sapphire CMOS circuitry possesses very high speed and low power consumption characteristics. While the ultrathin silicon-on-sapphire technology may be implemented in many well-known silicon circuit designs and devices, further innovative and advantageous circuit designs are possible that are enabled by the distinctive electrical and materials properties of the sapphire substrate.
Normally, radiation-induced charges in insulating layers are charged positively. This effect occurs because as most insulators are ionized by the radiation, the electron mobility in these layers is sufficiently high so that the created electrons are able to be swept out of the insulating layers by the electric fields which are present, leaving behind a net positive charge. It is thus generally true that the N-channel device is much more sensitive to ionizing radiation than the P-channel device. There have been a wide variety of approaches developed to “harden” NMOS transistors from these detrimental effects.
In an ultrathin silicon-on-sapphire transistor, the back insulator is sapphire as opposed to SiO2. The charging that occurs as a result of exposure to ionizing radiation is dramatically different from that observed in other forms of SOI technology. Under a certain set of bias conditions, exposure to ionizing radiation creates interface states at the sapphire/Si interface. These interface states are acceptor states (they are charged negatively when they are located below the Fermi level and neutral when they are above the Fermi level). The acceptor states are all located below midgap.
The effects of these below-midgap, radiation-induced acceptor states on the I-V characteristics of PMOS and NMOS ultrathin silicon-on-sapphire transistors are shown in FIGS. 1-4. FIG. 1 shows the energy band diagram 1 of a P-channel ultrathin silicon-on-sapphire transistor (electron energy vs. distance from surface) following exposure to radiation and the creation of the interface states 8. Region 2 is dielectric, region 3 is the silicon layer in the channel region, and region 4 is the insulator (the insulating sapphire substrate). FIG. 1 represents the case where the gate voltage is at the threshold voltage of the device. Curve 5 represents the conduction band edge, curve 6 represents the valence band edge, and curve 7 depicts the Fermi energy. It can be observed that at the back interface, the Fermi energy level is located in the region where the acceptor states are. Hence, as the device is swept below threshold, these acceptor states change charge as the Fermi level sweeps through them. This charging results in an I-V curve as shown in FIG. 2, an I-V curve for the P-channel transistor of FIG. 1, before (curve 10) and after (curve 9) exposure to radiation and the creation of interface states. Note that the curve 9 (the off state leakage current) is “stretched out” with respect to its pre-irradiated characteristics. Note also that the off state leakage (that current which flows with the gate at zero volts) increases dramatically after irradiation (curve 9). This effect represents a serious performance degradation for a MOS device; under normal conditions, MOS transistors are capable of offering a 109:1 ratio of on-state to off-state current.
By contrast, FIGS. 3 and 4 show the effect of these acceptor states on the I-V characteristics of a N-channel transistor. FIG. 3 shows the energy band diagram 11 of an N-channel transistor following exposure to radiation and the creation of interface states 8, where the gate voltage is at the threshold voltage of the device. Curve 13 represents the conduction band edge, curve 14 represents the valence band edge, and curve 15 depicts the Fermi energy. FIG. 4 shows the I-V curve for the N-channel transistor of FIG. 3, before (curve 16) and after (curve 17) exposure to radiation and the creation of interface states. At threshold, the Fermi level is above all of the states, and all of the acceptor states are occupied. As the gate voltage sweeps the device below threshold, the Fermi level does not move through the region of the bandgap where the states are located. Hence (as shown in FIG. 4) the net effect of the radiation-induced interface states on the N-channel transistor is only to cause a threshold shift 18 due to the fixed charge in these states and very little deleterious effect on the off-state leakage current.
The need to reduce off-state current in silicon-on-insulator devices in radiation exposed environments has been recognized, and some attempts to improve the situation have been reported.
U.S. Pat. Nos. 5,391,901 and 5,298,434 (“Selective recrystallization to reduce P-channel transistor leakage in silicon-on-sapphire CMOS radiation-hardened circuits”) describe “traditional” silicon-on-sapphire (SOS) P-channel devices. In contrast to the ultrathin silicon-on-sapphire structures described above which are of high crystalline quality, these earlier SOS devices have relatively high defect levels in the silicon overlayers, a result of the lattice mismatch between the silicon and the insulating substrate. U.S. Pat. Nos. 5,391,901 and 5,298,434 are directed to methods for balancing leakage currents in N-channel and P-channel devices by controlling the concentrations of these relatively high defect densities.
U.S. Pat. No. 4,633,289 (“Latch-up immune, multiple retrograde well high density CMOS FET”) and U.S. Pat. No. 5,428,239 (“Semiconductor device having retrograde well and diffusion-type well”) describe ion-implanted CMOS devices fabricated in bulk silicon, having a “retrograde” dopant concentration profile in the well region.
U.S. Pat. No. 4,054,895 (“Silicon-on-sapphire mesa transistor having doped edges”) describes silicon-on-sapphire transistors with channel edge regions (adjacent to the source regions) which are selectively doped with a high concentration of active carriers to raise the threshold voltage at the channel edge regions, thereby providing a higher breakdown voltage between the channel regions at the edge and the drain regions.
U.S. Pat. No. 5,360,752 (“Method to radiation harden the buried oxide in silicon-on-insulator structures”) describes a method to radiation harden silicon-on-insulator structures by implanting recombination-center-generating dopants into the buried oxide layer. In contrast to the high crystalline quality ultrathin silicon-on-sapphire structures described above, these SOS structures are formed by bonding and annealing a silicon device wafer to a thick oxide layer formed by wet oxidation of a first silicon substrate.
U.S. Pat. No. 3,882,350 (“Radiation hardening of MOS devices by boron”) describes radiation hardening of N-channel MOS devices by implanting a high dose of boron ions into the oxide region.
U.S. Pat. No. 5,220,192 (“Radiation-hardened CMOS structure using an implanted P guard structure and method for the manufacture thereof”); U.S. Pat. No. 4,797,721 (“Radiation hardened semiconductor device and method of making the same”); and U.S. Pat. No. 4,591,890 (“Radiation hard MOS devices and methods for the manufacture thereof”) describe approaches for radiation-hardening N-channel devices.
While significant progress has been made in producing radiation-hardened MOS devices, these prior art techniques do not recognize or address the effects of the charging that occurs as a result of exposure to ionizing radiation, in the silicon-insulator interface region of the NMOS transistor formed in ultrathin silicon-on-sapphire. Consequently, in order to take advantage of the desirable properties of ultrathin silicon-on-sapphire devices in radiation exposed environments, there is a need for an efficient method for eliminating or greatly reducing the radiation-induced off-state current in P-channel ultrathin silicon-on-sapphire transistors, and for forming silicon-on-sapphire devices that have reduced off-state current after irradiation.